1. Field of the Invention
The present invention relates to a semiconductor device featuring a plurality of wire-bonding pads, an interconnection pattern layer and a reinforcement pattern layer, and also relates to a pattern design apparatus for designing such both an interconnection pattern and a reinforcement pattern therefor.
2. Description of the Related Art
Usually, a semiconductor device has a multi-layered interconnection structure including a plurality of interconnection substructures, and each of the interconnection substructures has an interconnection formation insulating interlayer in which an interconnection pattern layer including a plurality of interconnections is formed, and a via-plug formation insulating interlayer in which a via-plug pattern layer including a plurality of via plugs is formed, with the interconnection pattern layers formed in the two adjacent interconnection formation insulating interlayers being suitably connected to each other through the intermediary of the plugs formed in the via-plug formation insulating interlayer therebetween.
The multi-layered interconnection structure includes an uppermost interconnection substructure having a plurality of wire-bonding electrode pads formed on a top surface thereof, and the wire-bonding electrode pads are suitably connected to the interconnection pattern layers included in the multi-layered interconnection structure. When the semiconductor device is mounted on a wiring board, each of the wire-bonding electrode pads is connected to an external electrode pad with a bonding wire, using a suitable wire bonding machine.
Conventionally, each of the insulating interlayers is formed as a silicon dioxide layer, and the interconnections and the via plugs are composed of aluminum.
With the recent advance of miniaturization and integration of semiconductor devices, the multi-layered interconnection structure becomes smaller, and thus the interconnections for signal transmission become thinner, resulting in delay of signal propagation in the interconnections, due to parasitic resistance of the signal transmission interconnections and parasitic capacitance involved in the signal transmission interconnections. In short, the miniaturization of the semiconductor devices has advanced to a degree in which a magnitude of a dielectric constant of the silicon dioxide layer and a magnitude of a resistance of the aluminum interconnections cannot be neglected.
Thus, there is a recent trend toward use of copper, exhibiting a smaller specific resistance than that of aluminum, for the interconnections, whereby it is possible to facilitate the signal transmission in the interconnections. Also, it has been proposed that an insulating interlayer, composed of a low-k material having a smaller dielectric constant than that of silicon dioxide, be substituted for the silicon dioxide layer, to thereby suppress the production of the parasitic capacitance. Note, for the low-k material, SiOC, SiC, SiOF, porous SiO2, porous SiOC or the like may be used.
Nevertheless, the low-k insulating interlayer exhibits an inferior physical strength to that of the silicon dioxide layer. Thus, the low-k insulating interlayer is susceptible to damage due to an impact which is produced when a bonding wire is bonded to each of the wire-bonding electrode pads by a wire-bonding machine.
In JP-2004-235416 A, it has been proposed that copper reinforcing elements are formed in a low-k insulating interlayer beneath a wire-bonding electrode pad so that the low-k insulating interlayer can be protected from being damaged when a bonding wire is bonded to the wire-bonding electrode pad by the wire-bonding machine.
Also, in JP-2004-039951 A, it has been proposed that both an interconnection pattern layer and a reinforcement pattern layer are formed in a low-k insulating interlayer so that the low-k insulating interlayer is wholly reinforced. In particular, the interconnection pattern layer includes a plurality of interconnections, and these interconnections are unevenly arranged and distributed over the low-k insulating interlayer so that blank areas, in which no interconnection is formed, are defined on the low-k insulating interlayer. On the other hand, the reinforcement pattern layer includes a plurality of reinforcing elements, and these reinforcing elements are arranged and distributed over the blank areas, whereby the low-k insulating interlayer is wholly reinforced.